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INTEGRATED CIRCUITS
DATA SHEET
UAA3580 Wideband code division multiple access frequency division duplex zero IF receiver
Objective specification Supersedes data of 2002 Oct 16 2002 Oct 30
Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 9.1 9.2 9.3 9.4 10 10.1 10.2 10.3 11 12 13 14 15 16 FEATURES APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description FUNCTIONAL DESCRIPTION RF receiver front-end and RF VCO Channel filter and AGC RF VCO RF LO section RF fractional-N synthesizer PLL Clock PLL Control OPERATING MODES Basic operating mode AGC gain look-up table RF PLL synthesizer Clock PLL synthesizer PROGRAMMING Serial programming bus Data format Register contents LIMITING VALUES THERMAL CHARACTERISTICS DC CHARACTERISTICS AC CHARACTERISTICS SERIAL BUS TIMING CHARACTERISTICS APPLICATION INFORMATION 17 18 18.1 18.2 18.3 18.4 18.5 19 20 21 PACKAGE OUTLINE SOLDERING
UAA3580
Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS
2002 Oct 30
2
Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
1 FEATURES 3 GENERAL DESCRIPTION
UAA3580
* Low noise wide dynamic range for zero IF receivers * 79 dB gain control range; in steps of 1 dB * Channel filters * 96 dB voltage gain * Fully integrated fractional-N synthesizer with AFC control capability * Fully integrated RF VCO with integrated supply voltage regulator * Fully differential design to minimize crosstalk * Supply voltage from 2.4 to 3.3 V * 3-wire serial interface bus * HVQFN24 package. 2 APPLICATIONS
The UAA3580 is a BiCMOS integrated circuit receiver intended for the Third Generation Partnership Project (3GPP) specification for the Universal Mobile Telecommunication System (UMTS). The circuit is specially designed for the Frequency Division Duplex (FDD) mode of the Wide Code Division Multiple Access (WCDMA) that operates in the 2110 to 2170 MHz band. The UAA3580 contains the whole analog receive chain from Radio Frequency (RF) Low Noise Amplifier (LNA) to baseband IQ outputs including a channel filter, a complete RF Phase-Locked Loop (PLL) with a fully integrated Voltage Controlled Oscillator (VCO), and a clock PLL that generates a programmable UMTS system clock from an external 26 MHz reference signal.
* WCDM-FDD receiver for GSM hand-portable equipment * Dual mode GSM/GPRS/EDGE/UMTS handset. 4 QUICK REFERENCE DATA SYMBOL VCCA VDDD Tamb 5 analog supply voltage digital supply voltage ambient temperature PARAMETER MIN. 2.6 1.6 -30 TYP. - - - MAX. 3.3 2.8 +70 UNIT V V C
ORDERING INFORMATION TYPE NUMBER PACKAGE VERSION NAME HVQFN24 DESCRIPTION plastic, heatsink very thin quad flat package; no leads 24 terminals; body 4 x 4 x 0.90 mm SOT616-1
UAA3580HN
2002 Oct 30
3
Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
6 BLOCK DIAGRAM
UAA3580
handbook, full pagewidth
REFIN
19
UAA3580HN
RF SIGMA DELTA FRACTIONAL-N RF SIGMA DELTA FRACTIONAL-N
18
REXT
VCCA(SYN)
20
DIVIDE-BY-2
17
UMTSCLKO
CPCLKO VCCA(CP) RFCPO
21 22 23 RF VCO
VCO
16
VDDD
15 SERIAL INTERFACE 14 13
EN CLK DATA
CAPVCOREG VCOGND VCCA(RF) RFGND RFIP RFIN IFGND RXCEN VCCA(IF)
24 1 2 3 4 5 6 7 8
VCO REGULATOR
DIVIDE-BY-2
MIXER
12 11
QN QP
LNA
MIXER
10 9
IN IP
FCA236
Fig.1 Block diagram.
2002 Oct 30
4
Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
7 7.1 PINNING INFORMATION Pinning
UAA3580
10 IN
12 QN 13 DATA 14 CLK 15 EN 16 VDDD 17 UMTSCLKO 18 REXT REFIN 19
FCA237
IFGND 6 RFIN 5 RFIP 4
UAA3580HN
RFGND 3 VCCA(RF) 2 VCOGND 1 RFCPO 23 VCCA(CP) 22 CAPVCOREG 24 VCCA(SYN) 20 CPCLKO 21
Fig.2 Pin configuration.
2002 Oct 30
5
11 QP
handbook, full pagewidth
RXCEN
VCCA(IF) 8
7
9
IP
Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
7.2 Pin description HVQFN24 package PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 die pad RF VCO ground analog supply voltage for the RF receiver RF receiver ground RF positive input RF negative input IF section ground receiver chip enable input analog supply voltage for the IF section differential receive baseband positive in-phase output differential receive baseband negative in-phase output differential receive baseband positive in-quadrature output differential receive baseband negative in-quadrature output serial bus data input serial bus clock input serial bus enable input digital supply voltage UMTS system clock output external charge pump biasing resistor connection reference clock input analog supply voltage for the synthesizer charge pump clock output analog supply voltage for the charge pump section RF charge pump output decoupling capacitor for the VCO regulator ground DESCRIPTION
UAA3580
Table 1
SYMBOL VCOGND VCCA(RF) RFGND RFIP RFIN IFGND RXCEN VCCA(IF) IP IN QP QN DATA CLK EN VDDD UMTSCLKO REXT REFIN VCCA(SYN) CPCLKO VCCA(CP) RFCPO CAPVCOREG
2002 Oct 30
6
Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
8 FUNCTIONAL DESCRIPTION 8.5
UAA3580
RF fractional-N synthesizer PLL
The receiver consists of an RF receiver front-end, an RF VCO, a channel filter, Automatic Gain Control (AGC), a RF fractional-N synthesizer PLL, a clock PLL, a Power-up reset circuit and a 3-wire serial programming bus. 8.1 RF receiver front-end and RF VCO
A high performance RF fractional-N synthesizer PLL is included on-chip which enables the frequency of the RF VCO to be synthesized. The frequency is set via the 3-wire serial programming bus. The PLL is based on Sigma-Delta () fractional-N synthesis that enables the required channel frequency, including Automatic Frequency Control (AFC) from a free running external 26 MHz GSM reference frequency, to be obtained. Very low close in-phase noise is achieved which allows a wider PLL loop bandwidth and a shorter settling time. The programmable main dividers are controlled by a second-order () modulus controller. They divide the RF VCO signals down to frequencies of 26 MHz (in programmable 12 Hz steps). Their phase is then compared in a digital Phase/Frequency Detector (PFD) to the 26 MHz reference clock signal. The phase error information is fed back to the RF VCO via the charge pump circuit that `sources' into or `sinks' current from the loop filter capacitor, thus changing the VCO frequency so that the loop is finally brought into phase-lock. The RF synthesizer division range enables an external reference frequency of 13 to 26 MHz to be used. 8.6 Clock PLL
The front-end receiver converts the aerial RF signal from WCMDA (2.11 to 2.17 GHz) band down to a Zero Intermediate Frequency (ZIF). The first stage is a differential low noise amplifier matched to 50 using an external balun. The LNA is followed by an IQ down-mixer which consists of two mixers in parallel but driven by quadrature out-of-phase LO signals. The In phase (I) and Quadrature phase (Q) ZIF signals are then low-pass filtered, to provide protection from high frequency offset interference, and fed into the channel filter. 8.2 Channel filter and AGC
The front-end zero IF I and Q outputs are applied to the integrated low-pass channel filter with a provision for 4 x 8 dB gain steps in front of the filter. The filter is a self-calibrated fifth-order low-pass filter with a cut-off frequency around 2.4 MHz. Once filtered the zero IF I and Q outputs are further amplified with provision for 47 x 1 dB steps and DC offset compensation. The zero IF output buffer provides close rail-to-rail output signal. 8.3 RF VCO
The RF VCO is fully integrated and self-calibrated on manufacturing tolerances. It consists of 16 different frequency ranges that are selected internally, depending on the frequency programmation. It covers the necessary bandwidth of 4.22 to 4.34 GHz and is tuned via the RF charge pump and external loop filter. An internal supply voltage regulator using the pin CAPVCOREG as external decoupling capacitor supplies the RF VCO and minimizes parasitic coupling and pushing. The regulator and the RF VCO are turned on by the RXCEN signal. 8.4 RF LO section
The clock PLL is based on SD fractional-N synthesis that allows the UMTS system clock, including AFC from a non-corrected external 26 MHz GSM reference frequency, to be obtained. The PLL comprises a fully integrated RC VCO. The PLL output is a low harmonic content waveform, the frequency of which can be programmed to 15.36, 30.72 or 61.44 MHz. The default value is 30.72 MHz. 8.7 Control
The RF LO section covering the 4.22 to 4.34 GHz band is driven by the internal RF VCO module. It includes the LO buffering for the RF PLL and a divide-by-two circuit to generate the quadrature LO signals to drive the RX IQ down-mixer.
The control of the chip is done via the 3-wire serial bus and pin RXCEN. At power-up the clock PLL section is automatically enabled, the other sections are enabled when the RXCEN signal is set HIGH (also via the 3-wire bus). The power-up signal is detected on pin VDDD when the voltage rises. The VDDD pin, if the supply voltage is maintained, enables the programming parameters to be retained in memory.
2002 Oct 30
7
Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
9 9.1 OPERATING MODES Basic operating modes IDLE SYN RX 9.2 Table 2 Selection of operating mode SYNON 0 1 1 AGC gain look-up table 0 0 1
UAA3580
MODE
RXON
The circuit can be powered up into different operating modes, depending on the control bits RXON and SYNON, via the 3-wire bus. This defines three main modes called IDLE, SYN and RX mode. The voltage level applied to pin RXCEN must be set HIGH to enable the device. The VCO and the PLL sections are enabled in SYN mode. In the RX mode every section is enabled (receive part, VCO and PLL sections). Table 3 AGC8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 2002 Oct 30 AGC gain look-up table AGC7 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 AGC6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AGC5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AGC4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AGC3 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 8
The AGC gain is set via the AGC[8:0] bits; see Table 3.
AGC2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
AGC1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
AGC0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
ATTENUATION FROM MAXIMUM GAIN (dB) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
AGC8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AGC7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AGC6 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 AGC5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 AGC4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AGC3 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 AGC2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 AGC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 AGC0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
UAA3580
ATTENUATION FROM MAXIMUM GAIN (dB) 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
2002 Oct 30
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Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
AGC8 0 0 0 0 0 0 0 0 0 AGC7 0 0 0 0 0 0 0 0 0 AGC6 0 0 0 0 0 0 0 0 0 AGC5 0 0 0 0 0 0 0 0 0 AGC4 0 0 0 0 0 0 0 0 0 AGC3 1 0 0 0 0 0 0 0 0 AGC2 0 1 1 1 1 0 0 0 0 AGC1 0 1 1 0 0 1 1 0 0 AGC0 0 1 0 1 0 1 0 1 0
UAA3580
ATTENUATION FROM MAXIMUM GAIN (dB) 71 72 73 74 75 76 77 78 79
The AGC[8:0] code required to program the AGC attenuation (AGCatt) can be calculated from the following formulas: AGC[8:0] = (511 - AGCatt)B if 0 < AGCatt < 11 AGC[8:0] = (391 - AGCatt)B if 12 < AGCatt < 19 AGC[8:0] = (271 - AGCatt)B if 20 < AGCatt < 27 AGC[8:0] = (151 - AGCatt)B if 28 < AGCatt < 35 AGC[8:0] = (95 - AGCatt)B if 36 < AGCatt < 43 AGC[8:0] = (151 - AGCatt)B if 44 < AGCatt < 51 AGC[8:0] = (95 - AGCatt)B if 52 < AGCatt < 59 AGC[8:0] = (135 - AGCatt)B if 60 < AGCatt < 67 AGC[8:0] = (79 - AGCatt)B if 68 < AGCatt < 79 Where (X)B is the binary code of the integer X.
2002 Oct 30
10
Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
9.3 RF PLL synthesizer Table 4 Clock mode
UAA3580
The RF fractional-N synthesizer is set via the 3-wire bus with the FRAC and CH chains. CH sets the integer divider ratio and FRAC the fractional divider ratio. They both provide the LO frequency in accordance with the following equation: N RX f RFLO = f ref x ---------- + K frac(RX) 2 Where K frac(RX) 1 1 = ------- x K RX + -- 22 2 2
RXCEN CLKon CLKoff 1 0 1 X(4) Notes 1 1 0 X(4) 0 0 0 1
DESCRIPTION CLKPLL synthesizer enabled (default) CLKPLL synthesizer disabled; note 1 CLKPLL synthesizer disabled; note 2 CLKPLL synthesizer disabled; note 3
Where KRX is the integer value of FRAC[21:0], NRX is the integer value of CH[8:0] and fref is the external frequency reference applied to pin REFIN. Example: to obtain a fRFLO frequency of 2.14 GHz with an error less than fPLL NRX must be set to 164 and Kfrac(RX) to 1290555 if the reference frequency is 26 MHz. It should be noted that some particular frequencies can be obtained in two ways; NRX = x and Kfrac(RX) = 0.25 provides the same frequency as NRX = x - 1 and Kfrac(RX) = 0.75 9.4 9.4.1 Clock PLL synthesizer AFC MODE
1. Hard power-down of the clock PLL done with RXCEN. 2. Power-down achieved via the 3-wire bus, reset by RXCEN. 3. Power-down achieved via the 3-wire bus, no effect by RXCEN in this mode. This mode will be reset if VDDD is not maintained. 4. X = don't care. 9.4.3 CLOCK PLL OUTPUT DIVIDER
The clock PLL is based on the SD fractional-N synthesizer that allows to derive the UMTS system clock including AFC from a non-corrected external 26 MHz only GMS reference. The clock PLL frequency with the AFC correction word is given by the following equation: 9 + K AFC f CLKPLL = f ref x ---------------------- - 2 231 AFC Where K AFC = --------- + -----------512 2 21 AFC represents the integer value of AFC[11:0] and fref is the external reference frequency applied to pin REFIN. 9.4.2 CLOCK PLL MODES
The clock PLL output divider ratio is set in accordance with Table 5. Table 5 CLKoff 1 0 0 0 0 Note 1. X = don't care. Clock mode; note 1 CLK1 X 0 0 1 1 CLK0 X 0 1 0 1 DESCRIPTION UMTSCLKO output disabled clock divider ratio set to default clock divider ratio set to 2 clock divider ratio set to 4 clock divider ratio set to 8
The clock PLL synthesizer is controlled by bits CLKon and CLKoff. At power-up the clock PLL synthesizer is automatically on when pin RXCEN is set HIGH. The control, done with CLKon, will be reset at the rising edge of RXCEN. For application which do not require the UMTS clock system, the clock PLL can be powered-down with bit CLKoff set to logic 1.
2002 Oct 30
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Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
10 PROGRAMMING 10.1 Serial programming bus 10.2 Data format
UAA3580
A simple 3-wire unidirectional serial bus is used to program the circuit. The 3 lines are DATA, CLK and EN. The data sent to the device is loaded in bursts framed by EN. Programming clock edges are ignored until EN goes active LOW. The programmed information is loaded into the addressed latch when EN goes HIGH (inactive). This is allowed when CLK is in either state without causing any consequences to the data register. Only the last 21 bits serially clocked into the device are retained within the programming register. Additional leading bits are ignored, and no check is made on the number of clock pulses. The fully static CMOS design uses virtually no current when the bus is inactive. It can always capture new programming data even during Power-down of the synthesizer. 10.3 Register contents Register bit allocation CONTROL BITS 20 19 18 17 16 15 14 13 12 11 10
Data is entered with the most significant bit first. The leading bits make up the data field, while the trailing four bits are an address field. The address bits are decoded on the rising edge of EN. This produces an internal load pulse to store the data in the address latch. To ensure that data is correctly loaded on first power-up, EN should be held LOW and only taken HIGH after having programmed an appropriate register. To avoid erroneous divider ratios, the pulse is inhibited during the period when data is read by the frequency dividers. This condition is guaranteed by respecting a minimum EN pulse width after data transfer.
Table 6
ADDRESS 9 8 7 6 5 4 3 0 0 2 0 0 1 1 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1
for test purposes only; all bits must be set to zero for normal operation; this is a forbidden address for test purposes only; all bits must be set to zero for normal operation; this is a forbidden address FRAC[15:0] CH[8:0] 0 0 Table 7 0 0 0 0 AFC[11:0] Description of symbols used in Table 6 SYMBOL SYNON RXON AGC CH FRAC AFC CLKoff CKO 1 1 9 6 22 12 1 2 BITS 3-wire bus 3-wire bus automatic gain control integer division ratio for the RF PLL DESCRIPTION AGC[8:0] FR[21:16] 1 CKO[1:0] 1 1 CLKoff
SYNON 0 SYNON 0 RXON CLKon 0 0
fractional division ratio for the RF PLL automatic frequency control for the clock PLL clock PLL disabled integer division ratio for the clock PLL
2002 Oct 30
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Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
Table 8 Register preset condition CONTROL 20 0 0 0 0 0 0 19 0 0 0 0 0 1 18 0 0 0 0 0 0 17 0 0 0 0 0 0 16 0 0 0 0 0 1 15 0 0 0 0 1 0 14 0 0 0 0 1 1 13 0 0 0 0 1 0 12 0 0 0 0 1 0 11 0 0 0 0 1 1 10 0 0 0 0 1 1 9 0 0 0 0 1 1 8 0 0 0 0 1 0 7 0 0 0 0 1 0 6 0 0 0 0 1 0 5 0 0 0 1 1 0 4 0 0 0 0 0 0 3 0 0 0 0 0 0
UAA3580
ADDRESS 2 0 0 1 1 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1
11 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDDD VCCA Ptot Tamb Tstg PARAMETER digital supply voltage analog supply voltage total power dissipation ambient temperature storage temperature CONDITIONS MIN. -0.3 -0.3 - -30 -40 TYP. - - - - - MAX. +2.8 +3.3 300 +80 +150 UNIT V V mW C C
12 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air; on a 4 layer PCB and with soldered exposed die pad VALUE 36 UNIT K/W
2002 Oct 30
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Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
13 DC CHARACTERISTICS VCCA = 2.6 V; VCCA(CP) = 2.6 V;Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VCCA VDDD ICCA(tot) analog supply voltage digital supply voltage total analog supply current receive mode; note 1 receive mode; note 2 synthesizer mode; note 3 standby mode; note 4 sleep mode; note 5 ICCA(RF) ICCA(IF) ICCA(SYN) ICCA(CP) IDDD VO(IQ)(CM) analog supply current for the RF VCO section analog supply current for the RX section analog supply current for the synthesizer analog supply current for the charge pump digital supply current on pins VCCA(RF), VCCA(IF), VCCA(CP) and VCCA(SYN) 2.6 1.6 - - - - - - - - - - 0.5(VIN + VIP) or 0.5(VQP + VQN); note 6 1.15 2.8 1.8 52 45 25 12 10 19 16 15 0.9 1.1 PARAMETER CONDITIONS MIN. TYP.
UAA3580
MAX.
UNIT
3.3 2.8 63 54 30 15 50 - - - - - 1.35
V V mA mA mA mA A mA mA mA mA mA
Baseband IQ section; pins IN, IP, QP and QN IQ common mode output voltage 1.25 V
RF VCO section; pin CAPVCOREG VO(CAPVCOREG) output voltage CLKPLL section; pin UMTSCLKO VO(UMTSCLKO) VREXT output voltage - Rext = 1.8 k - 0.8 - - V - 2 - V
Reference voltage; pin REXT reference voltage for the charge pump 360 mV
Control section; pins DATA, CLK, EN and RXON VIH VIL Notes 1. Receive mode: All circuits are active. 2. Receive mode: All circuits are active with the clock PLL off (CLKoff = 1). 3. Synthesizer mode: RF PLL and clock PLL are active. 4. Standby mode: Clock PLL is active. 5. Sleep mode: RXCEN set LOW, DATA, CLK and EN are in high-impedance. 6. Receive mode: DC voltage supplied from the IC. HIGH-level input voltage LOW-level input voltage 0.9 - - - - 0.3 V V
2002 Oct 30
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Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
14 AC CHARACTERISTICS VCCA = 2.6 V; Tamb = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - 170 1 -10 3.2 -20 -15 TYP.
UAA3580
MAX.
UNIT
RF receiver inputs; pins RFIN and RFIP fi(RF) Ri Ci s11 F CP1 IP3 RF input frequency input resistance input capacitance input power matching noise figure 1 dB compression point input referred 3rd-order intercept point with external balun in receive mode with maximum gain in receive mode with maximum gain in receive mode with maximum gain; interference 20 MHz away from channel bandwidth 2.11 - - - - -23 -18 2.17 - - - 4 - - GHz pF dB dB dBm dBm
IP2
input referred 2nd-order intercept point
in receive mode with 37 maximum gain; interferers 190 MHz away from channel bandwidth at 15 MHz offset - 92 12 - - -0.5 - peak error RL(diff) = 10 k; THD < 3% - 0.75
42
-
dBm
n Gv(max) Gv(min) AGCtot Gstep(AGC) AGCtot(lin) Gv(IQ) Vo(max) Io(max)
phase noise
- 96 17 79 1 - - - - -
-135 100 22 - - +0.5 0.5 5 - -
dBc/Hz
Baseband IQ section; pins IP, IN, QP and QN maximum voltage gain minimum voltage gain total AGC range AGC gain step total AGC linearity voltage gain mismatch between the I and Q paths quadrature phase error between the I and Q paths maximum output voltage per pin maximum output current per pin differential output offset voltage -3 dB high-pass corner frequency -3 dB low-pass corner frequency group delay variation 2nd-order high-pass frequency 5th-order low-pass frequency 100 kHz < fo < 2 MHz dB dB dB dB dB dB deg V A
Vo(p-p) = 1.75 V at 1 MHz; 650 RL(diff) = 10 k; CL(diff) = 20 pF -20 10 2.25 -
Voffset(diff) HP-3dB LP-3dB d(g)
- 15 2.4 260
+20 20 2.55 -
mV kHz MHz ns
2002 Oct 30
15
Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
SYMBOL LPF PARAMETER LPF attenuation CONDITIONS fi = 5 MHz fi = 10 MHz fi = 15 to 60 MHz RF synthesizer; pin RFCPO fRFLO fcomp(RF) fPLL n Isink Isource Vo(CP) K Ileak(CP) synthesizer frequency RF comparison frequency frequency resolution close-in-phase noise sink current source current charge pump output voltage PFD gain fcomp = 13 to 26 MHz fcomp = 26 MHz at 2 kHz offset Rext = 1.8 k; THD = 1% Rext = 1.8 k; THD = 1% charge pump current within specified range Rext = 1.8 k; THD = 1% 2.11 - 0.05 - - 170 170 0.4 27 -1 - 26 - - -85 200 200 - 32 - 2.17 - - 6.2 -80 230 230 MIN. 39 72 91 TYP. 42 75 94 - - -
UAA3580
MAX.
UNIT dB dB dB
GHz MHz ppm Hz dBc/Hz A A V A/rad A
VCCA - 0.4 37 +1
charge pump leakage current over full charge pump in off state voltage range
N RX 1 1 Fractional-N synthesizer; f RFLO = f ref x ---------- + K frac(RX) where K frac(RX) = ------- x K RX + -- 22 2 2 2 N Kfrac fRF GVCO Vtune fVCC tcal(VCO) fCLKPLL fcomp fPLL AFCcor Isink Isource Vo(CP) K Ileak(CP) integer divider ratio fractional divider ratio 130 0.25 - - - 70 - - - 122.88 13 - 30 200 200 - 32 - 507 0.75
Integrated RF VCO; pin RFCPO RF frequency VCO gain tuning voltage pushing VCO calibration time after RXON = LO HI VCPCLKO = 0 to 3.3 V fref = 26 MHz Rext = 1.8 k; THD = 1% Rext = 1.8 k; THD = 1% charge pump current within specified range Rext = 1.8 k; THD = 1% VRFCPO = 0 to 3.3 V VRFCPO = 1.3 V 4.22 50 0.4 - - - 0.477 - 170 170 0.4 27 -1 4.34 90 VCCA - 0.4 tbf 35 GHz MHz/V V MHz/V s MHz MHz ppm ppm A A V A/rad A
CLKPLL synthesizer; pin CPCLKO synthesizer frequency comparison frequency frequency resolution AFC correction range sink current source current charge pump output voltage PFD gain - - - 230 230 VCCA - 0.4 37 +1
charge pump leakage current over full charge pump in off state voltage range
2002 Oct 30
16
Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
SYMBOL PARAMETER CONDITIONS MIN. TYP.
UAA3580
MAX.
UNIT
N + K AFC 231 AFC Fractional-N synthesizer; f CLKPLL = f ref x ----------------------- where K AFC = --------- + ------------ 2 512 2 21 N KAFC fVCO GVCO Vtune fUMTSCLKO N n integer divider ratio fractional divider ratio - 0.4512 9 - - 15 - 30.72 4 - - - - 0.4532
Integrated CLKPLL VCO; pin CPCLKO CLKPLL frequency VCO gain tuning voltage VCPCLKO = 0 to 3.3 V VCPCLKO = 1.3 V 100 12 0.4 140 23 VCCA - 0.4 61.44 8 -90 -110 - dBc/Hz dBc/Hz V MHz MHz/V V
Output CLKPLL buffer; pin UMTSCLKO frequency range divider ratio close-in-phase noise phase noise Vo(p-p) output voltage (peak-to-peak value) at 2 kHz offset for 30.72 MHz at 3.84 MHz offset for 30.72 MHz RL = 10 k 15.36 2 - - 1 MHz
Low noise crystal amplifier; pin REFIN fREF Vi(REF)(rms) Ri(REF) Ci(REF) reference frequency input voltage (RMS value) input resistance input capacitance fREF = 26 MHz fREF = 26 MHz 13 50 - - - - tbf tbf 26 400 - - MHz mV k pF
2002 Oct 30
17
Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
15 SERIAL BUS TIMING CHARACTERISTICS VCCA = 2.6 V; VCCA(CP) = 2.6 V; VDDD = 1.6 V; Tamb = 25 C; unless otherwise specified. SYMBOL Serial clock; pin CLK ti(r) ti(f) Tcyc Enable; pin EN td(START) td(END) tW tsu;EN tsu;DATA th;DATA delay to rising clock edge delay from last falling clock edge minimum inactive pulse width enable set-up time to next clock 200 100 400 200 - - - - - - - - - - - - input rise time input fall time clock period - - 67 - - - 20 20 - PARAMETER MIN. TYP.
UAA3580
MAX.
UNIT
ns ns ns
ns ns ns ns
Register serial input data; pin DATA input data to clock set-up time input data to clock hold time 25 25 ns ns
handbook, full pagewidth
tsu;DAT
th;DAT Tcyc
ti(f)
ti(r)
td(END) tsu;EN
CLK
DATA
MSB
LSB
ADDRESS
EN tW
MGU575
td(START)
Fig.3 Serial bus timing diagram.
2002 Oct 30
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VCOGND VCCA(RF) RFGND RFIP RFIN IFGND 1 2 3 4 5 6 7 8 9 10 11 12
16 APPLICATION INFORMATION
Philips Semiconductors
Wideband code division multiple access frequency division duplex zero IF receiver
antenna or switch
BATTERY
ceramic duplexer isolator 9 10
8
7
6
5 4 3 LC MATCH ICTL EN
UAA3592
11 12 13 14
Vdet
2 1 15
Vreg
16
VCCA(SYN) REFIN
CAPVCOREG
VCCA(CP)
VCCA(SYN)
VCCA(CP)
CPCLKO
VCOTUNE
VDDD
CAPVCOREG
RFCPO
CPGND
24
23
22
21
20
19 18 17 16 REXT UMTSCLKO VDDD EN CLK DATA REFGND 13 14 15
12
11
10
9
8
7 6 5 4
SAW
differential to single-ended
VCCA(RF) RFON RFOP RFGND VCCA(IF) LC MATCH AND BIAS CHOKES
UAA3580
15 14 13
UAA3581
16 17 18 19 20 21 22 23 24
IFGND
3 2 1
Objective specification
VCCA(IF)
RXCEN
EN
UMTSCLKO
GSMCLKO
REFIN
QN
DATA
CLK
IP
IN
QP
TCEN
handbook, full pagewidth
QN
IP
IN
QP
FCA238
UAA3580
Fig.4 Application diagram.
Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
17 PACKAGE OUTLINE HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm
UAA3580
SOT616-1
D
B
A
terminal 1 index area A A1 E c
detail X
e1
1/2 e
C b 12 vMCAB wMC 13 e y1 C y
e 7 L 6
Eh
1/2 e
e2
1
18
terminal 1 index area
24 Dh 0
19 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.1 3.9 Dh 2.25 1.95 E (1) 4.1 3.9 Eh 2.25 1.95 e 0.5 e1 2.5 e2 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT616-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22
2002 Oct 30
20
Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
18 SOLDERING 18.1 Introduction to soldering surface mount packages
UAA3580
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 18.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 18.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2002 Oct 30
21
Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
18.5 Suitability of surface mount IC packages for wave and reflow soldering methods
UAA3580
SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
2002 Oct 30
22
Philips Semiconductors
Objective specification
Wideband code division multiple access frequency division duplex zero IF receiver
19 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
UAA3580
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 20 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 21 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403506/02/pp24
Date of release: 2002
Oct 30
Document order number:
9397 750 10632

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